1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a metal-oxide-semiconductor device for an electrostatic discharge protection circuit.
2. Description of Related Art
Electrostatic discharge is a phenomenon caused by the movement of static electricity from the surface of a non-conductive object. A human walking over a carpet may generate several hundred to several thousand volts of static electricity even if the ambient relative humidity (RH) is high. More than ten thousand volts may be produced if the surrounding relativity humidity is low. A typical station for packaging or testing semiconductor devices may be charged from several hundred up to several thousand volts of static electricity in an unscreened environment. Therefore, when the aforementioned charged body (a human body or a station) is in contact with a wafer, static electricity may discharge through the wafer in an electrostatic discharge (ESD). The sudden surge in power during the electrostatic discharge is often a main cause for the damage of semiconductor devices on the wafer.
To protect the semiconductor devices on a wafer against possible electrostatic discharge, various types of electrostatic discharge protection methods have been developed. The most common method deploys special hardware to clamp down the discharge. In other words, an electrostatic discharge protection circuit is set up between an internal circuit and each bonding pad. In general, a metal-oxide-semiconductor (MOS) transistor whose gate is grounded is used as a clamping device for ESD.
FIG. 1 is a schematic cross-sectional view of the MOS device for a conventional ESD protection circuit. The MOS device in FIG. 1 includes a p-type substrate 100, a gate structure 102, an n-type source region 104a and an n-type drain region 104b. The gate structure 102 is disposed on the substrate 100. The gate structure 102 includes a gate dielectric layer 106 and a gate conductive layer 108. The gate conductive layer 108 is disposed over the substrate 100 and the gate dielectric layer 106 is sandwiched between the substrate 100 and the gate conductive layer 108. The n-type source region 104a and the n-type drain region 104b are disposed within the substrate 100 on each side of the gate structure 102. Furthermore, the gate structure 102 and the source region 104a are coupled to a common voltage terminal 110.
In the aforementioned MOS device, the drain region 104b, the substrate 100 and the source region 104a together form a parasitic bipolar junction transistor (BJT) 112. The drain region 104b is the collector, the substrate is the base and the source region 104a is the emitter of the bipolar junction transistor 112. Consequently, the discharge current IESD in an ESD entering through the drain region 104b can be channeled to the common voltage terminal 110 (for example, a ground terminal) via the parasitic bipolar junction transistor 112.
However, with just one parasitic bipolar junction transistor connected to the MOS device, the parasitic bipolar junction transistor may be overloaded when an excessive discharge current and flows into the ESD protection circuit. Ultimately, the ESD protection circuit may fail to protect the internal devices.